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HCF40102B
8-STAGE PRESETTABLE SYNCHRONOUS 2 DECADE BCD DOWN COUNTERS
s
s
s s s s
s s
SYNCHRONOUS OR ASYNCHRONOUS PRESET MEDIUM -SPEED OPERATION : fCL =3.6MHz (Typ.) at VDD = 10V CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40102BEY HCF40102BM1 T&R HCF40102M013TR
DESCRIPTION HCF40102B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40102B consists of an 8-stage synchronous down counter with a single output that is active when the internal count is zero. This device is configured as two cascaded 4-bit BCD counters. It has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO DETECT output are active-low logics. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER PIN CONNECTION
ENABLE (CI/CE) input is high. The CARRY-OUT/ ZERO DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET ENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 represent two 4-bit BCD words. When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (9910) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control
September 2002
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inputs are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 clock pulses long. INPUT EQUIVALENT CIRCUIT HCF40102B may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. PIN DESCRIPTION
PIN No 1 2 3 4, 5, 6, 7, 10, 11, 12, 13 9 14 15 8 16 SYMBOL CLOCK CLEAR CI/CE J0 to J7 APE CO/ZD SPE VSS VDD NAME AND FUNCTION Clock Input (LOW to HIGH edge triggered) Asynchronous Master Reset Input (Active Low) Terminal Enable Input Jam Inputs Asynchronous Preset Enable Inputs(Active Low) Terminal Count Output (Active Low) Synchronous Preset Enable Input (Active Low) Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
CONTROL INPUTS PRESET MODE CLR H H H H L APE H H H L X SPE H H L X X CI/CE H L X X X Synchronous Inhibit Counter Count Down Preset on Next Positive Clock Transition Preset Asynchronously Clear to Maximum Count ACTION
Asynchronous
X : Don't Care Clock connected to Clock input Synchronous Operation : changes occur on negative to positive clock transitions.
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HCF40102B
LOGIC DIAGRAM
LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7
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HCF40102B
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 300 130 95 200 90 65 650 300 200 375 180 100 100 50 40 150 90 40 160 80 50 180 80 60 140 70 50 100 40 30 1.4 3.6 4.8 Max. 600 260 190 400 180 130 1300 600 400 750 360 200 200 100 80 ns Unit
tPHL tPLH Propagation Delay Time Clock To Out tPHL tPLH Propagation Delay Time Carry In/counter Enable To Output tPHL tPLH Propagation Delay Time Asynchronous Preset Enable To Output tPHL tPLH Propagation Delay Time Clear To Output tTHL tTLH Transition Time
ns
ns
ns
ns
tW
Clock Pulse Width
tW
Clear Pulse Width
tW
APE Pulse Width
tsetup
SPE Setup Time
tsetup
JAM Setup Time
fCL
Maximum Clock Input Frequency
300 180 80 320 160 100 360 160 120 280 140 100 200 80 60 0.7 1.8 2.4
ns
ns
ns
ns
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF40102B
TYPICAL APPLICATIONS DIVIDE BY "N" COUNTER SYNCHRONOUS CASCADING
MICROPROCESSOR INTERRUPT TIMER
SYNCHRONOUS CASCADING
MICROPROCESSOR INTERRUPT TIMER
* An Output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the parallel clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry-out delay. This spike is eliminated by gating the output of the last device with the clock as shown.
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HCF40102B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
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HCF40102B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF40102B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF40102B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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